Eighth: Dynamic Window and Linear-Buffer IR

Abstract. Eighth (e1) emits ARM64 directly from Forth with a fixed six-deep register window and streaming codegen. The swarm’s plan: expand the window into X22–X28, spill with post-indexed STP/LDP, and stop streaming. A packed 64-bit Linear-Buffer IR enables LICM on DO…LOOP, vector pairing, and window-aware liveness. Peepholes for Neoverse V2 fuse address math into loads and stores so matmul128 and kmp stop paying a Load–ALU–Store chain on every array tick.

Dynamic window + post-indexed spilling

The current prologue allocates a fixed frame and parks live values in X6–X16. Spills are pre-indexed LDR/STR at static offsets, so a growing stack needs extra ADD. The replacement takes a live-var-count from analysis, expands into X22–X28, and uses LDP/STP Xn, Xn+1, [SP], #16 on the hot path. The post-index is the increment; the extra ADD dies.

Linear-Buffer IR

Streaming emit cannot hoist. The IR is a contiguous array of 64-bit entries: 8-bit flags, 8-bit opcode, two 16-bit registers, 16-bit meta. DO…LOOP becomes a loop block with an explicit header. Invariant ops (no loop-carried dependence) move to the header — LICM, the missing pass that matmul128 and kmp need. Vector pairing and window-aware liveness sit on the same buffer.

Neoverse V2 peepholes

The pattern to kill: LDR → ALU (ADD/SUB) → STR where the ALU is addressing. Fuse the address into the memory instruction. Deep pipeline plus L1 D-cache latency make that chain the dominant tax on the four named benches (matmul128, kmp, fft, countingsort). Strength reduction and software pipelining come after the IR exists; they are not first.

This is the implementable remainder of the metacognitive chain: not homotopy, a buffer and a window.

Source report. Summarized from docs/QWEN-OPTIMIZATION-SUMMARY.md, docs/E1-OPTIMIZATION-PLAN.md in the hive tree. This page is the paper. The report remains the primary.